View VT1616_488410.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

VIA Technologies Incorporated
Features
* * * * * * * * * * * * * * *
VT1616
6-Channel AC97 Codec with S/PDIF
Description
AC'97 2.2 compliant codec VIA Technologies' VT1616TM 20-bit | audio codec conforms to the AC'97 2.2 and S/PDIF 20-bit, stereo ADC and 6-channel stereo DACs Output specifications. The VT1616 integrates 1 Hz resolution VSR on all channels Sample Rate Converters on all channels and can be Integrated IEC958 line driver for S/PDIF output adjusted in 1Hz increments. There is a provision in S/PDIF compressed digital or LPCM audio out hardware for down-mixing the 6 channels into Hardware downmix option to 2 channels stereo when only two end points are available. The ADC DC removal for removing recording white noise analog mixer circuitry integrates a stereo enhancement to provide a pleasing 3D surround 4-bit 3D stereo expansion for simulated surround sound effect for stereo media. This codec is 4 stereo, 2 mono analog line-level inputs designed with aggressive power management to Second line-level output with volume control achieve low power consumption. When used with a 3.3V analog supply, power consumption is further External Audio Amplifier Control reduced. The primary applications for this part are Low Power consumption mode desktop and portable personal computers Exceeds Microsoft(R) WHQL logo requirements multimedia subsystems. However, it is suitable for 3.3V digital, 3.3 or 5V analog power supply any system requiring 6-channel audio output for home theater systems at competitive prices. 48-pin LQFP small footprint package
CENTER + LFE PCM OUT REAR SURROUND PCM OUT PC_BEEP PHONE FRONT PCM OUT SRC LINE CD VIDEO AUX MIC1 MIC2 SYNC BIT_CLK SDATA_OUT SDATA_IN RESET#
M U X
SRC
DAC
VOL
MUTE
LFE/CENTER
SRC
DAC
M U X
VOL VOL
MUTE MUTE
VOLUME /MUTE MASTER VOLUME
LNL/SR_OUT
MUTE MUTE MUTE MUTE MUTE MUTE
LINE_OUT
DAC
VOL VOL VOL VOL VOL
3D
M U X
MONO VOLUME
MONO_OUT
VOL +20dB
VOL
M U X MASTER INPUT VOLUME
AC'97 Digital Interface
ADC
XTL_IN XTL_OUT
OSC
PCM IN
SRC S/PDIF_OUT
Figure 1. Functional Block Diagram
Revision 1.5, October 11, 2002 1 Data Sheet
VT1616 6-Channel AC97 Codec with S/PDIF
(c) VIA Technologies, Inc., 2000, 2001, 2002. All Rights Reserved.
VIA TECHNOLOGIES PRODUCTS ARE NOT AUTHORIZED FOR, AND SHOULD NOT BE USED WITHIN, LIFE SUPPORT SYSTEMS OR NUCLEAR FACILTY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF VIA TECNOLOGIES, Inc. Life support systems are those intended to support or sustain life, and show failure to perform when used as directed can reasonably expect to result in personal injury or death. Nuclear facilities are those involved in the production, handling, use, storage, disposal, or any other activity involving fissionable materials or their waste products. The VIA Technologies logo is a trademark of VIA Technologies, Inc. All other trademarks referenced in this document are owned by their respective companies. VIA Technologies, Inc. believes the information contained herein to be correct at the time of the publication. The information is provided "AS IS" without warranty of any kind (expressed or implied). No responsibility is assumed by VIA Technologies, Inc. for the use of this information, nor infringements of patents or other rights of third parties. VIA Technologies, Inc. reserves the right to make changes at any time, without prior notice, to improve and supply the best possible product and is not responsible and does not assume any liability for misapplication or use outside the limits specified in this document. VIA Technologies provides no warranty for the use of its products and assumes no liability for errors contained in this document.
Contact Information US Office 940 Mission Court Fremont, CA 94539 USA Tel: (510) 687-4600 Fax: (510) 687-4654 Web: www.viatech.com Taiwan Office 8th Floor, No. 533 Chung-Cheng Road, Hsien-Tien Taipei, Taiwan ROC Tel: 886 (2) 2218-5452 Fax: 886 (2) 2218-5453 Web: www.via.com.tw
Revision 1.5, October 11, 2002
2
Data Sheet
VT1616 6-Channel AC97 Codec with S/PDIF
LNL/SR_OUT_R
LNL/SR_OUT_L
CENTER_OUT
48
47
46
45
44
43
42
41
40
39
DVCC1 XTL_IN XTL_OUT DGND1 SDATA_OUT BIT_CLK DGND2 SDATA_IN DVCC2 SYNC RESET# PC_BEEP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
38
37 36 35 34 33 32
MONO_OUT
SPDIF_OUT
LFE_OUT
AGND2
AVCC2
EAPD
ID1
ID0
NC
LINE_OUT_R LINE_OUT_L NC NC CAP2 NC AFLT2 AFLT1 VREF_OUT VREF AGND1 AVCC1
VT1616
31 30 29 28 27 26 25
PHONE
VIDEO_L
CD_L
LINE_IN_L
AUX_L
CD_GND
MIC1
VIDEO_R
CD_R
MIC2
Figure 2. Pin Diagram - 48-Pin LQFP
Revision 1.5, October 11, 2002
3
LINE_IN_R
AUX_R
Data Sheet
VT1616 6-Channel AC97 Codec with S/PDIF
Table 1. Pin Description
Pin #
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Symbol
DVCC1 XTL_IN XTL_OUT DGND1 SDATA_OUT BIT_CLK DGND2 SDATA_IN DVCC2 SYNC RESET# PC_BEEP PHONE AUX_L AUX_R VIDEO_L VIDEO_R CD_L CD_GND CD_R MIC1 MIC2 LINE_IN_L LINE_IN_R AVCC1 AGND1 VREF VREF_OUT AFLT1 AFLT2 NC CAP2 NC NC LINE_OUT_L LINE_OUT_R
Type
P I O P I I/O P O P I I I I I I I I I I I I I I I P P I O O O - - - - O O
Description
Digital Supply Voltage, 3.3V only 24.576 MHz Crystal or clock input 24.576 MHz Crystal Digital Ground AC'97 Serial Data Input Stream 12.288 MHz Serial Data Clock Digital Ground AC'97 Serial Data Output Stream Digital Supply Voltage, 3.3V only 48 KHz Fixed Rate Sync Pulse AC'97 Master Reset PC Speaker Beep Pass Through Telephony Subsystem Speakerphone Auxiliary Audio Left Channel Auxiliary Audio Right Channel Video Audio Left Channel Video Audio Right Channel CD Audio Left Channel CD Audio Analog Ground CD Audio Right Channel Desktop Microphone Second Microphone Line In Left Channel Line In Right Channel Analog Supply Voltage, 5V or 3.3V Analog Ground Reference Voltage Reference Voltage Output Left Channel Anti-Aliasing Filter Capacitor Right Channel Anti-Aliasing Filter Capacitor No Connect ADC Reference Voltage Capacitor No Connect No Connect Line Out Left Channel Line Out Right Channel
Revision 1.5, October 11, 2002
4
Data Sheet
VT1616 6-Channel AC97 Codec with S/PDIF
Table 1. Pin Description (continued...)
Pin #
37 38 39 40 41 42 43 44 45 46 47 48 Note:
Symbol
MONO_OUT AVCC2 LNL/SR_OUT_L NC LNL/SR_OUT_R AGND2 CENTER_OUT LFE_OUT ID0 ID1 EAPD SPDIF_OUT
Type
O P O - O P O O I I O I/O
Description
Mono Output Analog Supply Voltage, 5V or 3.3V Alternate Left Line Level out or Rear Channel Left No Connect Alternate Right Line Level out or Rear Channel Right Analog Ground Center Channel Output Low Frequency Effects Output Multiple Codec Select (Internal pull-up). Please see Table 5. Multiple Codec Select (Internal pull-up). Please see Table 5. External Power Amplifier Power Down PCM/Non-Audio Sony/Philips Digital I/F Output (Internal pull-up). If left floating, S/PDIF not implemented reported on 2Ah, bit 2 = "0"
The VT1616 supports +5V or +3.3V analog power supply. For best analog performance use a 5V analog supply. For maximum power savings use 3.3V for both analog and digital sections. You must use 3.3V as the digital supply. The digital I/Os are NOT 5V tolerant.
Revision 1.5, October 11, 2002
5
Data Sheet
VT1616 6-Channel AC97 Codec with S/PDIF
3.3V DVCC 10F 0.1F 10F 0.1F 0.1F 10F 0.1F 10F 5V AVCC Regulated power supply recommended for best analog performance
1 DVCC1 2 24.576MHz 22pF 22pF 3 XTL_IN XTL_OUT
9 DVCC2
25 AVCC1
38 AVCC2 ID1 ID0 46 45 1F LINE_OUT_L 35 1nF 47k LINE LEVEL OUTPUTS 1F 1k 1nF 47k LINE_OUT_R 36 1k Master Codec Select
1F 23 LINE INPUTS 1F 24 1F 18 1F CD INPUTS 1F 20 1F 16 VIDEO INPUTS 1F 17 1F 14 AUXILIARY INPUTS 1F 15 1F MIC1 IN 1F MIC2 IN 1F PHONE 47k PC BEEP 4.7k AVCC 3.3V DVCC SYNC BIT_CLK SDATA_OUT SDATA_IN RESET# 0.1F 12 2.7nF PC_BEEP 32 CAP2 0.1F 10 6 5 8 11 13 PHONE 22 MIC2 VREFOUT VREF 21 MIC1 AUX_R EAPD SPDIF_OUT 47 48 28 27 0.1F AUX_L VIDEO_R VIDEO_L CD_R LNL/SR_OUT_L LNL/SR_OUT_R 39 41 19 CD_GND MONO_OUT 37 CD_L 1F LINE_IN_R LINE_IN_L
1k MONO OUTPUT 1nF 47k
VT1616
CENTER_OUT LFE_OUT 43 44
Repeat circuits as above for the 4 surround channels
220 110 RCA coaxial S/PDIF
10F
10F
SYNC BIT_CLK SDATA_OUT SDATA_IN RESET# AFLT1 DGND1 4 DGND2 7 AGND1 26 AGND2 42 AFLT2
30 270pF NPO 29 270pF NPO
DC`97
Single point connection Board Digital Ground Board Analog Ground
Figure 3. Typical Connection Diagram
Revision 1.5, October 11, 2002 6 Data Sheet
VT1616 6-Channel AC97 Codec with S/PDIF Register Map
Index Register Name D15
- Mute Mute Mute Mute Mute Mute Mute Mute Mute Mute Mute - Mute - -
D14
SE4 - - - - - - - - - - - - - - -
D13
SE3 -
D12
SE2
D11
SE1
D10
SE0
D9
ID9
D8
ID8
D7
ID7 - - - - - - - - - - - - -
D6
ID6 - - - - - 20dB - - - - - - - - - -
D5
ID5 -
D4
ID4
D3
ID3
D2
ID2 MR2 MR2
D1
ID1
D0
ID0
00h 02h 04h 06h 0Ah 0Ch 0Eh 10h 12h 14h 16h 18h 1Ah 1Ch 20h 22h 26h 28h 2Ah 2Ch 2Eh 30h 32h 36h 38h 3Ah ... 5Ah 5Ch ... 7Ah 7Ch 7Eh
Reset Stereo Output Volume Alt. Line Output Vol. Mono Output Volume PC Beep Volume Phone Volume Mic In Volume Line In Volume CD In Volume Video In Volume Aux In Volume PCM Out volume Record Select Record Gain General Purpose 3D Control Power Down & Status Extended Audio ID Ext. Audio Stat/Control PCM Front DAC Rate Surround DAC Rate PCM LFE DAC Rate PCM LR ADC Rate LFE/Center Volume Surround Volume S/PDIF Control ... Test Control Register Special Control Reg. ... Vendor Reserved Vendor ID1 Vendor ID2
ML4 ML3 ML2 ML1 ML0 ML4 ML3 ML2 ML1 ML0 - - - - GL4 GL4 GL4 GL4 GL4 - - - - PR4 - PRJ - - - - GL3 GL3 GL3 GL3 GL3 - GL3 - - PR3 - - - - - GL2 GL2 GL2 GL2 GL2 SL2 GL2 - - PR2 - - - - - GL1 GL1 GL1 GL1 GL1 SL1 GL1 MIX - PR1 - - - - - - GL0 GL0 GL0 GL0 GL0 SL0 GL0
MR4 MR3 MR4 MR3
MR1 MR0 MR1 MR0
-
- - - - - - - - - - - 3D - PR5 - PRK
-
- - - - - - - - - - - - - - -
MM4 MM3 MM2 MM1 MM0 PV3 PV2 PV1 GN2 GN2 GR2 GR2 GR2 GR2 GR2 SR2 GR2 - DP2 ANL SPDIF SPDIF SR2 SR2 SR2 SR2 PV0 -
GN4 GN3 GN4 GN3 GR4 GR4 GR4 GR4 GR4 - - - - - - GR3 GR3 GR3 GR3 GR3 - GR3 - DP3 REF - - SR3 SR3 SR3 SR3
GN1 GN0 GN1 GN0 GR1 GR1 GR1 GR1 GR1 SR1 GR1 - DP1 GR0 GR0 GR0 GR0 GR0 SR0 GR0 - DP0
MS LPBK - PR0 - -
EAPD PR6 ID1 - ID0 -
DAC ADC - - SR1 SR1 SR1 SR1 VRA VRA SR0 SR0 SR0 SR0
LDAC SDAC CDAC
PRI SPCV
LDAC SDAC CDAC SSA1 SSA0 SR8 SR8 SR8 SR8 SR7 SR7 SR7 SR7 SR6 SR6 SR6 SR6 - - CC2 ... Res. Res. ... - S6 SR5 SR5 SR5 SR5 - - CC1 ... Res. Res. ... - S5 SR4 SR4 SR4 SR4
SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR15 SR14 SR13 SR12 SR11 SR10 SR9 Mute Mute V ... LVL Res. ... - F7 T7 - - - -
LFE4 LFE3 LFE2 LFE1 LFE0 Mute LSR4 LSR3 LSR2 LSR1 LSR0 Mute L ... CC6 ... CC5 ... CC4 ... Res. Res. ... - F0 T0 CC3 ... Res. Res. ... - S7
CNT4 CNT3 CNT2 CNT1 CNT0 RSR4 RSR3 RSR2 RSR1 RSR0 CC0 ... Res. Res. ... - S4 PRE ... IB1 Res. ... - S3 COPY /PCM PRO ... IB0 Res. ... - S2 ... Res. Res. ... - S1 ... Res. LBE ... - S0
-
... Res. Res. ... - F6 T6
SSR1 SSR0 ... ...
Res. LCTF STF BPDC DC Res. ... - F5 T5 Res. ... - F4 T4 Res. ... - F3 T3 Res. ... - F2 T2 Res. ... - F1 T1
REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0
In compliance with the AC `97 rev. 2.2 specification, all reserved or non-implemented register bits, non-implemented addresses, odd register addresses return 0 when read. Vendor specific registers 5Ah - 7Ah are reserved for special functions, testing and similar operations.
Revision 1.5, October 11, 2002
7
Data Sheet
VT1616 6-Channel AC97 Codec with S/PDIF Register Descriptions
Reset Register (Index 00h)
D15 - D14 SE4 D13 SE3 D12 SE2 D11 SE1 D10 SE0 D9 ID9 D8 ID8 D7 ID7 D6 ID6 D5 ID5 D4 ID4 D3 ID3 D2 ID2 D1 ID1 D0 ID0 Default 6D50h
The Reset register is used to configure the hardware to a known state or to read the ID code of the part. A code was assigned to VIA Technologies (27 = 11011h) for 3D Stereo Enhancement reflected in SE[4:0]. ID8 and ID6 are set to 1b to report that the ADC and DAC are 20-bit resolution respectively. The VT1616 supports an alternate line level out with independent volume control as reflected by ID4=1b. However, since pins 39 and 41 are shared with the Surround DAC outputs, register 5Ah, bit 15, LVL has to be set to "1". Writing data to this register will set all the mixer registers to their default values. For description of the bits set to 0b, refer to AC'97 Rev. 2.2 spec.
Stereo Output Control Register (Index 02h)
D15 Mute D14 - D13 - D12 ML4 D11 ML3 D10 ML2 D9 ML1 D8 ML0 D7 - D6 - D5 - D4 MR4 D3 MR3 D2 MR2 D1 MR1 D0 MR0 Default 8000h
Mute
Stereo Output Mute Control
"1" : "0" :
ML[4:0]
Mute enabled Mute disabled
Master Output (Left Channel) Volume Control
These five bits select the level of attenuation applied to the Left channel of the Stereo Output signal. The level of attenuation is programmable from 0dB to -46.5dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Table 2 on page 10 for details.
MR[4:0] Master Output (Right Channel) Volume Control
These five bits select the level of attenuation applied to the Right channel of the Stereo Output signal. The level of attenuation is programmable from 0dB to -46.5dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Table 2 on page 10 for details.
Revision 1.5, October 11, 2002
8
Data Sheet
VT1616 6-Channel AC97 Codec with S/PDIF
Alternate Line Output Control Register (Index 04h)
D15 Mute D14 - D13 - D12 ML4 D11 ML3 D10 ML2 D9 ML1 D8 ML0 D7 - D6 - D5 - D4 MR4 D3 MR3 D2 MR2 D1 MR1 D0 MR0 Default 8000h
Note: Pins 39 and 41 are shared with the Surround DAC outputs. LVL, register 5Ah, bit 15, has to be set to "1" Mute Stereo Output Mute Control
"1" : "0" :
ML[4:0]
Mute enabled Mute disabled
Alternate Line Output (Left Channel) Volume Control
These six bits select the level of attenuation applied to the Left channel of the Stereo Output signal. The level of attenuation is programmable from 0dB to -46.5dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Table 2 on page 10 for details.
MR[4:0] Alternate Line Output (Right Channel) Volume Control
These five bits select the level of attenuation applied to the Right channel of the Stereo Output signal. The level of attenuation is programmable from 0dB to -46.5dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Table 2 on page 10 for details.
Revision 1.5, October 11, 2002
9
Data Sheet
VT1616 6-Channel AC97 Codec with S/PDIF
Mono Output Control Register (Index 06h)
D15 Mute D14 - D13 - D12 - D11 - D10 - D9 - D8 - D7 - D6 - D5 - D4 D3 D2 D1 D0 Default 8000h MM4 MM3 MM2 MM1 MM0
Mute
Mono Output Mute Control
"1" : "0" :
MM[4:0]
Mute enabled Mute disabled
Mono Output Volume Control
These five bits select the level of attenuation applied to the Mono Output signal. The level of attenuation is programmable from 0dB to -46.5dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Table 2 on page 10 for details. Table 2. Stereo and Mono Output Attenuation
M4
0 1 2 3 4 5 .. .. 28 29 30 31 0 0 0 0 0 0 .. .. 1 1 1 1
M3
0 0 0 0 0 0 .. .. 1 1 1 1
M2
0 0 0 0 1 1 .. .. 1 1 1 1
M1
0 0 1 1 0 0 .. .. 0 0 1 1
M0
0 1 0 1 0 1 .. .. 0 1 0 1
Level (dB)
0.0 -1.5 -3.0 -4.5 -6.0 -7.5 .. .. -42.0 -43.5 -45.0 -46.5
PC Beep Input Volume Control Register (Index 0Ah)
D15 Mute D14 - D13 - D12 - D11 - D10 - D9 - D8 - D7 - D6 - D5 - D4 PV3 D3 PV2 D2 PV1 D1 PV0 D0 - Default 8000h
Mute
PC Beep Input Mute Control
"1" : "0" :
PV[3:0]
Mute enabled Mute disabled
PC Beep Input Volume Control
These four bits select the level of attenuation applied to the PC beep input signal. The level of attenuation is programmable from 0dB to -45dB in 3dB increments, providing a total of 16 programmable levels. The beep gain is set at 0dB when PV[3:0] = 0h. Even though the default of the input volume control is mute, as long as RESET# is active, PC Beep will be passively routed to the line outputs.
Revision 1.5, October 11, 2002 10 Data Sheet
VT1616 6-Channel AC97 Codec with S/PDIF
Phone Input Volume Control Register (Index 0Ch)
D15 Mute D14 - D13 - D12 - D11 - D10 - D9 - D8 - D7 - D6 - D5 - D4 GN4 D3 GN3 D2 GN2 D1 GN1 D0 GN0 Default 8008h
Mute
Phone Input Mute Control
"1" : "0" :
GN[4:0]
Mute enabled Mute disabled
Phone Input Volume Control
These five bits select the gain applied to the Phone Input signal. The gain is programmable from 34.5dB to 12dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Table 3 on page 14 for details.
Mic Input Volume Control Register (Index 0Eh)
D15 Mute D14 - D13 - D12 - D11 - D10 - D9 - D8 - D7 - D6 20dB D5 - D4 GN4 D3 GN3 D2 GN2 D1 GN1 D0 GN0 Default 8008h
Mute
Mic Input Mute Control
"1" : "0" :
20dB
Mute enabled Mute disabled
Mic Boost Control
"1" : "0" :
GN[4:0]
Fixed 20dB gain enabled Fixed 20dB gain disabled
Mic Input Volume Control
These five bits select the gain applied to the Mic Input signal. The gain is programmable from 34.5dB to 12dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Table 3 on page 14 for details.
Revision 1.5, October 11, 2002
11
Data Sheet
VT1616 6-Channel AC97 Codec with S/PDIF
Line Input Control Register (Index 10h)
D15 Mute D14 - D13 - D12 GL4 D11 GL3 D10 GL2 D9 GL1 D8 GL0 D7 - D6 - D5 - D4 GR4 D3 GR3 D2 GR2 D1 GR1 D0 GR0 Default 8808h
Mute
Line Input Mute Control
"1" : "0" :
GL[4:0]
Mute enabled Mute disabled
Left Channel Gain Control
These five bits select the gain applied to the LEFT channel of the Line Input signal. The gain is programmable from -34.5dB to 12dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Table 3 on page 14 for details.
GR[4:0] Right Channel Gain Control
These five bits select the gain applied to the RIGHT channel of the Line Input signal. The gain is programmable from -34.5dB to 12dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Table 3 on page 14 for details.
CD Input Control Register (Index 12h)
D15 Mute D14 - D13 - D12 GL4 D11 GL3 D10 GL2 D9 GL1 D8 GL0 D7 - D6 - D5 - D4 GR4 D3 GR3 D2 GR2 D1 GR1 D0 GR0 Default 8808h
Mute
CD Input Mute Control
"1" : "0" :
GL[4:0]
Mute enabled Mute disabled
Left Channel Gain Control
These five bits select the gain applied to the Left channel of the CD Input signal. The gain is programmable from -34.5dB to 12dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Table 3 on page 14 for details.
GR[4:0] Right Channel Gain Control
These five bits select the gain applied to the Right channel of the CD Input signal. The gain is programmable from -34.5dB to 12dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Table 3 on page 14 for details.
Revision 1.5, October 11, 2002
12
Data Sheet
VT1616 6-Channel AC97 Codec with S/PDIF
Video Input Control Register (Index 14h)
D15 Mute D14 - D13 - D12 GL4 D11 GL3 D10 GL2 D9 GL1 D8 GL0 D7 - D6 - D5 - D4 GR4 D3 GR3 D2 GR2 D1 GR1 D0 GR0 Default 8808h
Mute
Video Input Mute Control
"1" :
GL[4:0]
Mute enabled "0":Mute disabled
Left Channel Gain Control
These five bits select the gain applied to the Left channel of the Video Input signal. The gain is programmable from -34.5dB to 12dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Table 3 on page 14 for details.
GR[4:0] Right Channel Gain Control
These five bits select the gain applied to the Right channel of the Video Input signal. The gain is programmable from -34.5dB to 12dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Table 3 on page 14 for details.
Auxiliary Input Control Register (Index 16h)
D15 Mute D14 - D13 - D12 GL4 D11 GL3 D10 GL2 D9 GL1 D8 GL0 D7 - D6 - D5 - D4 GR4 D3 GR3 D2 GR2 D1 GR1 D0 GR0 Default 8808h
Mute
Auxiliary Input Mute Control
"1" :
GL[4:0]
Mute enabled "0":Mute disabled
Left Channel Gain Control
These five bits select the gain applied to the Left channel of the Auxiliary Input signal. The gain is programmable from -34.5dB to 12dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Table 3 on page 14 for details.
GR[4:0] Right Channel Gain Control
These five bits select the gain applied to the Right channel of the Auxiliary Input signal. The gain is programmable from -34.5dB to 12dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Table 3 on page 14 for details.
Revision 1.5, October 11, 2002
13
Data Sheet
VT1616 6-Channel AC97 Codec with S/PDIF
PCM Output Control Register (Index 18h)
D15 Mute D14 - D13 - D12 GL4 D11 GL3 D10 GL2 D9 GL1 D8 GL0 D7 - D6 - D5 - D4 GR4 D3 GR3 D2 GR2 D1 GR1 D0 GR0 Default 8808h
Mute
PCM Output Mute Control
"1" : "0" :
GL[4:0]
Mute enabled Mute disabled
Left Channel Gain Control
These five bits select the gain applied to the LEFT channel of the PCM Output signal. The gain is programmable from -34.5dB to 12dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Table 3 on page 14 for details.
GR[4:0] Right Channel Gain Control
These five bits select the gain applied to the RIGHT channel of the PCM Output signal. The gain is programmable from -34.5dB to 12dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Table 3 (below) on page 14 for details. Table 3. Programmable Mixer Input Gain Levels
G4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
G3
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
G2
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
G1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
G0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Level (dB)
12.0 10.5 9.0 7.5 6.0 4.5 3.0 1.5 0.0 -1.5 -3.0 -4.5 -6.0 -7.5 -9.0 -10.5 -12.0 -13.5 -15.0 -16.5 -18.0 -19.5 -21.0 -22.5 -24.0 -25.5 -27.0 -28.5 -30.0 -31.5 -33.0 -34.5
Revision 1.5, October 11, 2002
14
Data Sheet
VT1616 6-Channel AC97 Codec with S/PDIF
Record Select Register (Index 1Ah)
D15 - D14 - D13 - D12 - D11 - D10 SL2 D9 SL1 D8 SL0 D7 - D6 - D5 - D4 - D3 - D2 SR2 D1 SR1 D0 SR0 Default 0000h
SL[2:0]
Record Source Select (Left Channel)
These bits determine the record source for the left channel.
SL2 0 0 0 0 1 1 1 1 SL1 0 0 1 1 0 0 1 1 SL0 0 1 0 1 0 1 0 1 Left Record Source Mic CD (L) Video In (L) Aux In (L) Line In (L) Stereo Mix (L) Mono Mix Phone
SR[2:0]
Record Source Select (Right Channel)
These bits determine the record source for the right channel.
SR2 0 0 0 0 1 1 1 1 SR1 0 0 1 1 0 0 1 1 SR0 0 1 0 1 0 1 0 1 Right Record Source Mic CD (R) Video In (R) Aux In (R) Line In (R) Stereo Mix (R) Mono Mix Phone
Revision 1.5, October 11, 2002
15
Data Sheet
VT1616 6-Channel AC97 Codec with S/PDIF
Record Gain Control Register (Index 1Ch)
D15 Mute D14 - D13 - D12 - D11 GL3 D10 GL2 D9 GL1 D8 GL0 D7 - D6 - D5 - D4 - D3 GR3 D2 GR2 D1 GR1 D0 GR0 Default 8000h
Mute
Record Mute Control
"1" : "0" :
GL[3:0]
Mute enabled Mute disabled
Record Gain Control (Left Channel)
These four bits select the gain applied to the LEFT channel recording source. The gain is programmable from 0dB to 22.5dB in 1.5dB increments, providing a total of 16 programmable levels. The gain is set at 0dB when GL[3:0] = 0h.
GR[3:0] Record Gain Control (Right Channel)
These four bits select the gain applied to the RIGHT channel recording source. The gain is programmable from 0dB to 22.5dB in 1.5dB increments, providing a total of 16 programmable levels. The gain is set at 0dB when GR[3:0] = 0h.
General Purpose Register (Index 20h)
D15 - D14 - D13 3D D12 - D11 - D10 - D9 MIX D8 MS D7 LPBK D6 - D5 - D4 - D3 - D2 - D1 - D0 - Default 0000h
3D
3D Stereo Enhancement
"1" : "0" :
MIX
Enable 3D Disable 3D
Mono Output Mode
"1" : "0" :
MS
Mic Output Mono mix output
Microphone Select
"1" : "0" :
LPBK
Microphone 2 Microphone 1
Loopback Mode
For this bit to be valid, 5C_0 must be set to "1". See description of LBE on page 26. "1" : DAC/ADC Loopback enabled "0" : DAC/ADC Loopback disabled
Revision 1.5, October 11, 2002
16
Data Sheet
VT1616 6-Channel AC97 Codec with S/PDIF
3D Control Register (Index 22h)
D15 - D14 - D13 - D12 - D11 - D10 - D9 - D8 - D7 - D6 - D5 - D4 - D3 DP3 D2 DP2 D1 DP1 D0 DP0 Default 0000h
DP[3:0]
3D Depth Control
These four bits control the linear depth control of the 3D stereo enhancement built into the codec. The gain is programmable from 0% to 100% in 6.67% increments, providing a total of 16 programmable levels. The default value corresponds to no stereo enhancement. Table 4. 3D Depth Control
DP3
0 1 2 3 4 5 .. .. 12 13 14 15 0 0 0 0 0 0 .. .. 1 1 1 1
DP2
0 0 0 0 1 1 .. .. 1 1 1 1
DP1
0 0 1 1 0 0 .. .. 0 0 1 1
DP0
0 1 0 1 0 1 .. .. 0 1 0 1
Level (%)
0.0 6.67 13.33 20 26.67 33.33 .. .. 80 86.67 93.33 100
Revision 1.5, October 11, 2002
17
Data Sheet
VT1616 6-Channel AC97 Codec with S/PDIF
Power Down and Status Register (Index 26h)
D15 D14 D13 PR5 D12 PR4 D11 PR3 D10 PR2 D9 PR1 D8 PR0 D7 - D6 - D5 - D4 - D3 REF D2 ANL D1 DAC D0 ADC Default 0000h EAPD PR6
EAPD
Enable Amplifier Power Down
"1" : Powerdown External Power Amplifier "0" : External Power Amplifier active The signal polarity at pin 47, EAPD is identical to bit description.
PR[6:0] Power Down Mode Bits
These read/write bits are used to control the power down states of the VT1616. Each power down function bit is enabled by setting the respective bit high. Particularly, PR5 has no effect unless PR0, PR1 and PR4 are all set to "1". This implies that the codec can be woken up by a warm reset, because warm reset clears PR4, which in turn disables the function of PR5. The register bit, however will not be cleared by a warm reset. The power down modes controlled by each bit is described in the table below:
Bit
PR0 PR1 PR2 PR3 PR4 PR5 PR6
Function
ADC and Mux Powerdown DAC Powerdown Mixer Powerdown (VREF on) Mixer Powerdown (VREF off) AC Link Powerdown (BIT_CLK off) Internal Clock Disabled Alternate Line Out Powerdown
REF,ANL,ADC,DACStatus (READ Only) bits
These bits are used to monitor the readiness of some sections of the VT1616. Reading a "1" from any of these bits would be an indication of a "ready" state.
Bit
REF ANL DAC ADC
Status Bit
VREF at nominal level Mixer, Mux and Volume Controls ready DAC ready to accept data ADC ready to transmit data
Revision 1.5, October 11, 2002
18
Data Sheet
VT1616 6-Channel AC97 Codec with S/PDIF
Extended Audio ID Register (Index 28h)
D15 ID1 D14 ID0 D13 - D12 - D11 - D10 - D9 D8 D7 D6 D5 - D4 - D3 - D2 SPDIF D1 - D0 VRA Default 01Exh AMAP LDAC SDAC CDAC
The Extended Audio ID is a read only register that indicates the capabilities of the VT1616.
ID[1:0] (See Table below)
One primary and an additional codec may be supported as an option. Since the VT1616 codec has all six outputs implemented, the ID pin setting affects only the BIT_CLK direction and the register decoding. BIT_CLK output the power-up default. Setting the codec besides default changes BIT_CLK to input mode. As indicated by D9, AMAP=0, there is no need to change slot mappings. Table 5. Multiple Codec Mode Status Bits
ID1
0 0 1 1 Note:
ID0
0 1 0 1
Codec Mode
Primary Codec (default) Secondary Codec Invalid Invalid
The state of the ID pins is reported in reverse polarity on register 28h, bits D15 and D14. If you use this table to configure the codec via pins 45 and 46, use the inverse values. Please, refer to Figure 4 on page 27. BIT_CLK is an output for the primary codec and an input pin for the controller and secondary codecs. ID[1:0] pins with internal pull-up resistors defaults codec as primary codec.
AMAP
Slot/DAC mapping based on Codec ID
"0" :
xDAC
Feature not applicable since all possible channels are available on VT1616.
Multi-channel Output Capabilities
"1": LDAC, SDAC, CDAC report to the querying host that the codec has all six outputs implemented.
SPDIF Sony/Philips Digital Audio Interface
"1" : "0" :
VRA
Feature implemented in compliance to "S/PDIF Output for AC `97, Rev 1.0" Indicates that SPDIF_OUT pin 48 is left floating or pulled-high. It reflects the lack of external S/PDIF application circuitry.
Variable Sampling Rate PCM Audio
"1" :
Feature implemented in compliance to AC `97 2.2 Appendix A
Revision 1.5, October 11, 2002
19
Data Sheet
VT1616 6-Channel AC97 Codec with S/PDIF
Extended Audio Status/Control Register (Index 2Ah)
D15 - D14 - D13 PRK D12 PRJ D11 PRI D10 SPCV D9 - D8 D7 D6 D5 D4 D3 - D2 SPDIF D1 - D0 VRA Default 3800h LDAC SDAC CDAC SSA1 SSA0
PRx
Multi-channel Output Control
All three bits, PRK, PRJ, PRI behave similarly. When set to "0", the respective DAC(s) is (are) turned on. PRK is for LFE, PRJ for Surround (Rear pair), PRI for Center channel.
SPCV S/PDIF Configuration Valid (Read Only)
"0" : S/PDIF configuration (SSA, SSR, DAC rate, DRS) invalid (not supported) "1" : S/PDIF configuration (SSA, SSR, DAC rate, DRS) valid (supported)
xDAC Multi-channel Output Status (Read Only)
These read only bits, LDAC, SDAC, CDAC behave similarly. When they report "1", the respective DAC(s), LFE, Surround and Center is (are) ready.
SSA[1:0] S/PDIF Slot Assignment
These bits determine the S/PDIF data source from AC-link slot selection when SPDIF_OUT, pin 48 is low during reset (pulled low by external application circuit). If the S/PDIF application circuit is not implemented, these bits will return only 0. The default state reflects the pervasive design feature of common AC'97 digital controllers supporting slots 3 & 4. Slots 10 & 11 are expected to be used in the future to support concurrent 6 channels analog and 2 channel digital audio (compressed or LPCM).
SSA1 0 0 1 1 SSA0 0 1 0 1 S/PDIF Source Data AC-link slots 3 & 4 (front stereo pair, power-up default) AC-link slots 7 & 8 (surround pair) AC-link slots 6 & 9 (LFE & Center pair) AC-link slots 10 &11
SPDIF
Sony/Philips Digital Audio Interface Enable/Disable
"1" : "0" :
VRA
Set this bit to turn on the S/PDIF transmitter. The S/PDIF transmitter is off by default.
Variable Sampling Rate Mode control
"1" : "0" :
Enable VSR Fixed 48 KHz sampling rate
Revision 1.5, October 11, 2002
20
Data Sheet
VT1616 6-Channel AC97 Codec with S/PDIF
PCM Front and Center DAC Sample Rate Register (Index 2Ch)
D15 D14 D13 D12 D11 D10 D9 SR9 D8 SR8 D7 SR7 D6 SR6 D5 SR5 D4 SR4 D3 SR3 D2 SR2 D1 SR1 D0 SR0 Default BB80h SR15 SR14 SR13 SR12 SR11 SR10
SR[15:0]
Main stereo + Center or all DAC Sample Rate (in Hz)
16-bit unsigned value representing the sample rate in 1Hz resolution. The default value is 48 KHz (48000 = BB80h). This register controls all six DAC output rate providing a sample accurate synchronization among the channels. Registers 2Eh and 30h are read/writable but have no control over the Surround and LFE channels. They reflect 2Ch when read back.
PCM Surround DAC Sample Rate Register (Index 2Eh)
D15 D14 D13 D12 D11 D10 D9 SR9 D8 SR8 D7 SR7 D6 SR6 D5 SR5 D4 SR4 D3 SR3 D2 SR2 D1 SR1 D0 SR0 Default BB80h SR15 SR14 SR13 SR12 SR11 SR10
SR[15:0]
Surround DAC Sample Rate (in Hz)
16-bit unsigned alias value of 2Ch representing the sample rate in 1Hz resolution. The default value is 48 KHz (48000 = BB80h). This register has no physical control over the Surround pair DACs sampling rate.
PCM LFE DAC Sample Rate Register (Index 30h)
D15 D14 D13 D12 D11 D10 D9 SR9 D8 SR8 D7 SR7 D6 SR6 D5 SR5 D4 SR4 D3 SR3 D2 SR2 D1 SR1 D0 SR0 Default BB80h SR15 SR14 SR13 SR12 SR11 SR10
SR[15:0]
LFE DAC Sample Rate (in Hz)
16-bit unsigned alias value of 2Ch representing the sample rate in 1Hz resolution. The default value is 48 KHz (48000 = BB80h). This register has no physical control over the LFE DAC's sampling rate.
PCM ADC Sample Rate Register (Index 32h)
D15 D14 D13 D12 D11 D10 D9 SR9 D8 SR8 D7 SR7 D6 SR6 D5 SR5 D4 SR4 D3 SR3 D2 SR2 D1 SR1 D0 SR0 Default BB80h SR15 SR14 SR13 SR12 SR11 SR10
SR[15:0]
ADC Sample Rate (in Hz)
16-bit unsigned value representing the sample rate in 1Hz resolution. The default value is 48 KHz (48000 = BB80h).
Revision 1.5, October 11, 2002
21
Data Sheet
VT1616 6-Channel AC97 Codec with S/PDIF
LFE and Center Channels Output Volume Control Register (Index 36h)
D15 Mute D14 - D13 - D12 D11 D10 D9 D8 D7 D6 - D5 - D4 D3 D2 D1 D0 Default 8080h LFE4 LFE3 LFE2 LFE1 LFE0 Mute CNT4 CNT3 CNT2 CNT1 CNT0
Mute
Individual Output Mute Control
"1" : "0" :
LFE[4:0]
Mute enabled Mute disabled
LFE Output Volume Control
These five bits select the level of attenuation applied to the Low Frequency Effect channel. The level of attenuation is programmable from 0dB to -46.5dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Table 2 on page 10 for details.
CNT[4:0] Center Channel Output Volume Control
These five bits select the level of attenuation applied to the Center channel. The level of attenuation is programmable from 0dB to -46.5dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Table 2 on page 10 for details.
Revision 1.5, October 11, 2002
22
Data Sheet
VT1616 6-Channel AC97 Codec with S/PDIF
Surround Channels Output Volume Control Register (Index 38h)
D15 Mute D14 - D13 - D12 D11 D10 D9 D8 D7 D6 - D5 - D4 D3 D2 D1 D0 Default 8080h LSR4 LSR3 LSR2 LSR1 LSR0 Mute RSR4 RSR3 RSR2 RSR1 RSR0
Note: Pins 39 and 41 are shared with the Alternate Line Level Out, main stereo DAC outputs. LVL, register 5Ah, bit 15, has to be set to "0" for this register to be effective on the same volume control block. Mute Individual Output Mute Control
"1" : "0" :
LSR[4:0]
Mute enabled Mute disabled
Left Surround (Rear) Channel Output Volume Control
These five bits select the level of attenuation applied to the Left Surround channel. The level of attenuation is programmable from 0dB to -46.5dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Table 2 on page 10 for details.
RSR[4:0] Right Surround (Rear) Channel Output Volume Control
These five bits select the level of attenuation applied to the Right Surround channel. The level of attenuation is programmable from 0dB to -46.5dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Table 2 on page 10 for details.
Revision 1.5, October 11, 2002
23
Data Sheet
VT1616 6-Channel AC97 Codec with S/PDIF
S/PDIF Control Register (Index 3Ah)
D15
V
D14
-
D13
SSR1
D12
SSR0
D11
L
D10
CC6
D9
CC5
D8
CC4
D7
CC3
D6
CC2
D5
CC1
D4
CC0
D3
PRE
D2
D1
D0
PRO
Default x000h
COPY /PCM
This read/write register controls the S/PDIF functionality when SPDIF bit at 28h_2 reports S/PDIF is implemented. It will return 0000h when SPDIF_OUT, pin 48 left floating or pulled high. If S/PDIF is implemented for the final product, it will read 2000h at power-up. The register manages the bit fields propagated as channel status (or subframe in the V case). With the exception of V, this register should only be written when the S/PDIF transmitter is disabled (SPDIF bit at 2Ah_2 is "0"). This ensures that control and status information start up correctly at the beginning of S/PDIF transmission.
V Validity
This bit affects the "Validity flag", bit 28 transmitted in each subframe and enables the S/PDIF transmitter to maintain connection during error or mute conditions. "0" : If a valid Left/Right pair was received via AC-link and transmitted through S/PDIF, the Validity bit should be reset to "0" "1" : Tags both samples as invalid by setting bit 28, "Validity flag" to "1"
SSR[1:0] S/PDIF Sample Rate
These bits declare the available S/PDIF transmitter clock rate (64*fs).
SSR1 0 0 1 1 SSR0 0 1 0 1 S/PDIF Sample Rate Not Available Reserved 48 KHz (default) Not Available
L
Generation Level
Programmed according to IEC standards.
CC[6:0] Category Code
Programmed according to IEC standards.
PRE Preemphasis
"1" : Indicates filter preemphasis is 50/15s. "0" : Default is no Preemphasis.
COPY Copyright
"1" : Indicates copyright is asserted. "0" : Copyright is not asserted (default).
/PCM Non-Audio Samples
"1" : Set this bit for transmitting non-PCM audio samples such as AC-3. "0" : Indicates samples are linear PCM suitable for direct conversion to audio playback. .
PRO Professional
"1" : Set Professional mode. Set this bit in conjunction with /PCM bit (above) for AC-3. "0" : Indicates Consumer mode (default).
Revision 1.5, October 11, 2002
24
Data Sheet
VT1616 6-Channel AC97 Codec with S/PDIF
Vendor Reserved Register (Index 5Ah)
D15 LVL D14 Res. D13 Res. D12 LCTF D11 D10 D9 DC D8 Res. D7 Res. D6 Res. D5 Res. D4 Res. D3 IB1 D2 IB0 D1 Res. D0 Res. Default 8200h STF BPDC
Res.
Test Mode Bits
These read/write bits are used for testing the digital modes of the audio codec. Do not access them during Normal operation.
LVL Alternate Line Level Out to Surround Out
The VT1616 powers up with pins 39 and 41 assigned to the Front channel DACs as described in the AC97 Revision 2.2 specification. When this bit is to "0", the output pins get assigned to the Rear stereo DAC pair with an independent volume control.
LCTF Downmix LFE and Center DAC outputs to the Front channels
The VT1616 is capable of downmixing the LFE and the Center channel outputs to the Line_Out pins using internal hardware. Without processing overhead, it is possible to listen to all the channels without loss of audio cues. The relative SPL (Sound Pressure Level) for these channels are retained as meant by the digital audio content mastering engineer. This is ideal for 4-channel applications.
STF Downmix Surround DAC outputs to the Front channels
The VT1616 is capable of downmixing the Rear channel outputs to the Line_Out pins using internal hardware besides the LFE and the Center. This is useful when multichannel material needs to be played back on a stereo end point like headphones. Without processing overhead, it is possible to listen to all the channels without loss of audio cues. The relative SPL (Sound Pressure Level) for these channels are retained as meant by the digital audio content mastering engineer. This is ideal for 2-channel applications when LCTF and STF are both activated at the same time.
BPDC ADC DC-offset Removal Control
The default setting of "0" ensures that the circuit is disabled at power up. When set to "1", the DCoffset cancellation circuit will be enabled. This helps to maximize recording quality by removing white noise.
DC DC-offset Removal Capability
This read only bit indicates that the codec incorporates DC-offset removal hardware.
IB[1:0] Analog Current Setting Bits
Normally these bits should be left at default when analog operating at 5V supply. The four possible settings adjust the power consumption of the analog section. The power-up default 00b sets the codec for the best overall analog performance at 5V. At 3.3V analog supply, 10b should be set for the lowest power instead of default 00b. This mode is desirable for system designs with limited power budget such as battery operated portable devices. Setting to 11b puts the codec to its best AA mixer performance overall.
IB1
0 0 1 1
IB0
0 1 0 1
Analog Current Setting
Normal (1X) Reduced (4/5X) Power Miser (2/3X) Enhanced (4/3X)
Revision 1.5, October 11, 2002
25
Data Sheet
VT1616 6-Channel AC97 Codec with S/PDIF
Vendor Reserved Register (Index 5Ch)
D15 Res. D14 Res. D13 Res. D12 Res. D11 Res. D10 Res. D9 Res. D8 Res. D7 Res. D6 Res. D5 Res. D4 Res. D3 Res. D2 Res. D1 Res. D0 LBE Default 0000h
LBE
Loopback Test Mode Engage
When set to "1", it will allow the functionality of 20h_7, Loopback test mode.
Res. Test Mode Bits
These read/write bits are used for testing the digital modes of the audio codec. Do not access them during Normal operation. Vendor Identification Register (Index 7Ch)
D15 F7 D14 F6 D13 F5 D12 F4 D11 F3 D10 F2 D9 F1 D8 F0 D7 S7 D6 S6 D5 S5 D4 S4 D3 S3 D2 S2 D1 S1 D0 S0 Default 4943h
The upper and lower byte of this register (index 7Ch), in conjunction with the upper byte of index register 7Eh, make up the vendor identification code for the VT1616. The Vendor ID Code (in ASCII format) is equal to "ICE", where:
F[7:0] S[7:0] T[15:8] Upper Byte (Index 7Ch) D[15:8] = I Lower Byte (Index 7Ch) D[7:0] = C Upper Byte (Index 7Eh) D[15:8] = E
Revision Identification Register (Index 7Eh)
D15 T7 D14 T6 D13 T5 D12 T4 D11 T3 D10 T2 D9 T1 D8 T0 D7 D6 D5 D4 D3 D2 D1 D0 Default 4551h REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0
The upper byte of this register is used in conjunction with index register 7Ch to make up the Vendor ID code for the VT1616. The lower byte identifies VT1616 and its revision code.
T[15:8] REV[7:0] See description in Vendor Identification Register. Revision ID
"51":
VT1616 identification and revision number
Note: As a reference, other valid Rev IDs associated with VIA AC'97 products are: "01h" for the VT1611 (ICE1230), "11h" for the VT1611A (ICE1232), and "14h" for the ICE1232A (this part has no corresponding VIA part number).
Revision 1.5, October 11, 2002
26
Data Sheet
VT1616 6-Channel AC97 Codec with S/PDIF Multiple Codec Example
The primary codec provides the master BIT_CLK. The secondary codec, if any, and the controller, will use this clock to work in synchronous mode. Note that the ID[1:0] pins are internally pulled up; therefore, it is necessary to pull the ID[1:0] pins low to set the codec as secondary. Notice that the state of the ID[1:0] pins are reflected in reverse polarity as shown on Table 5 on page 19. See Reg. 28h for more details.
DC `97
SYNC BIT_CLK SDATA_OUT RESET# SDATA_IN0 SDATA_IN1
AC `97 ~ Primary
SYNC BIT_CLK SDATA_OUT RESET# SDATA_IN
ID1 ID0
1 1
AC `97 ~ Secondary
SYNC BIT_CLK SDATA_OUT RESET# SDATA_IN
ID1 ID0
1 0
Figure 4. Multiple Codec Example
Revision 1.5, October 11, 2002
27
Data Sheet
VT1616 6-Channel AC97 Codec with S/PDIF Power Management
The VT1616 may be placed in several power down states using the power down control bits located in index register 26h. Table 6 lists the power down states accessible through this register. Table 6. Power Down Mode Bits
Bit
PR0 PR1 PR2 PR3 PR4 PR5 PR6 Note:
Function
ADC and Mux Powerdown DAC Powerdown Mixer Powerdown (VREF on) Mixer Powerdown (VREF off) AC Link Powerdown (BIT_CLK off) Internal Clock Disabled Alternate Line Out Powerdown
Registers maintain values in sleep mode (PR4 write) and wake up with a warm reset (register values) or a cold reset (default values). Power Down and Status register (index 26h) read action verifies stability before power down write action occurs.
PR0=1
PR1=1
PR2=1
PR4=1
Normal
ADC's OFF PR0
DAC's OFF PR1
Analog OFF PR2 / PR3
Digital I/F OFF PR4
Shut Off
PR0=0 & ADC=1
PR1=0 & DAC=1
PR2=0 & ANL=1
Warm Reset
Default Ready=1 Cold Reset
Note: In this example, the Analog Mixer has been disabled, but VREF is still on.
Figure 5. AC'97 Power Down / Power Up Procedure Complete power down of the AC'97 device is achieved by sequential writes to the Power Down and Status Control Register (Index 26h) as follows: Normal Operations: ADC's and Input Mux: DAC's: Analog Mixer: VREF_OUT: AC-link: Internal Clocks: Alt. Line Out:
Revision 1.5, October 11, 2002
PR[6:0] = 00h PR0 = 1 (write) PR1 = 1 (write) PR2 = 1 (write) PR3 = 1 (write) PR4 = 1 (write) PR5 = 1 (write) PR6 = 1 (write)
28 Data Sheet
VT1616 6-Channel AC97 Codec with S/PDIF Power Management (continued...)
Cold Reset PR0=1 PR1=1 PR4=1 PR5=1
Normal PR0=0 & ADC=1
ADC's OFF PR0 PR1=0 & DAC=1
DAC's OFF PR1
Digital I/F OFF PR4
Shut Off Oscillator Off
Warm Reset
Cold Reset
Note: To wake up the codec, a warm reset can be used; PR4 is reset to zero upon either reset. PR5 can only be cleared by a cold reset.
Figure 6. AC'97 Power Down Procedure with Analog Section Still Active
Test Mode Operation
ATE Test Mode: (PCB in-circuit Testing of the VT1616)
ATE Test mode is entered when the SDATA_OUT signal is sampled at the rising edge of the RESET# signal. In this mode, the SDATA_IN and BIT_CLK pins are placed in a high impedance (Hi-Z) state as shown on Table 14 on page 39. This mode of operation doesn't occur under normal operating conditions.
Vendor Test Mode:
Vendor Test mode is entered when the SYNC signal is sampled during the rising edge of the RESET# signal as shown on Table 15 on page 39. This mode of operation doesn't occur under normal operating conditions.
Revision 1.5, October 11, 2002
29
Data Sheet
VT1616 6-Channel AC97 Codec with S/PDIF Absolute Maximum Ratings
Table 7. Limits
(AGND = DGND = 0V)
Symbol
- - - - - - - - -
Caution:
Parameter
Digital Power Supplies (DVCC) Analog Power Supplies (AVCC) Input Current per Pin Output Current per Pin Digital Input Voltage Analog Input Voltage Total Power Dissipation Ambient Temperature Storage Temperature
Min
-0.3 -0.3 -10 -15 -0.3 -0.3
Typ
Max
4.0 6.0 10 15 DVCC+0.3 AVCC+0.3
Unit
V V mA mA V V mW
270 -55 -65 110 150
C C
Exceeding any of these limits can cause permanent failure of the device and will void any claims against product quality.
Recommended Operating Conditions
Table 8. Limits
(AGND = DGND = 0V)
Symbol
- - - -
Parameter
Digital Power Supplies (DVCC) Analog Power Supplies (AVCC), preferred Analog Power Supplies (AVCC), for low power apps Operating Ambient Temperature
Min
3.135 4.75 3.135 0
Typ
3.3 5 3.3
Max
3.465 5.25 3.465 70
Unit
V V V C
Revision 1.5, October 11, 2002
30
Data Sheet
VT1616 6-Channel AC97 Codec with S/PDIF Performance Specifications
Table 9. Analog Performance Characteristics (+5V Power)
TA=25C, AVCC = 5V 5%, DVCC = 3.3V 5%; AGND = DGND =0V; 10k / 50pF Load; FS = 48 KHz, 0dB = 1VRMS; BW: 20Hz ~ 20 KHz, 0dB Attentuation, IB[1:0]=00 (power up default), as targeted for a 2-layers VT5542 ACR card
Symbol
Parameter
Full Scale Input Voltage: Line Inputs Mic Inputs (20dB = 0) Mic Inputs (20dB = 1) Full Scale Output Voltage: Analog S/N: Analog Frequency Response Digital S/N: Total Harmonic Distortion: DACs ADC LINE_IN to LINE_OUT (DA) DAC to LINE_OUT D/A and A/D Frequency Response: Transition Band: Stop Band: Stop Band Rejection: Out-of-Band Rejection Group Delay Power Supply Rejection Ratio (1 KHz) Input Channel Crosstalk Spurious Tone Reduction Attenuation, Gain Step Size Input Impedance Input Capacitance VREFOUT DACs ADC DACs ADC DACs ADC DACs ADC Line Outputs Mono Output CD to LINE_OUT Other to LINE_OUT
Min
Typ
1.0 1.0 0.1 1.0 1.0 96 96
Max
Unit
VRMS VRMS VRMS VRMS VRMS dB dB
20 85 75 88 91 -94 -82 20 20 19,200 19,200 28,800 28,800 75 75 -40
20,000
Hz dB dB
-74 -74 19,200 19,200 28,800 28,800 infinity infinity
dB dB Hz Hz Hz Hz Hz Hz dB dB dB
1 -40 -70 -100 1.5 10 45 15 2.4
ms dB dB dB dB k pF V
Note:
VIL = 0.8V, VIH = 2.4V Analog Frequency Response has 1dB limits SNR (measured as THD+N) of rms output level with 1 KHz full-scale input to rms output level with all zeros into digital input Measured "A wtd" over a 20Hz ~ 20 KHz bandwidth (AES17-1991 Idle Channel Noise or EIAJ CP-307 SNR) THD: 0dB gain, 20 KHz BW, Fs = 48 KHz, -3dB "large" signal A/D and D/A Frequency Response has 0.25dB limits Stop Band Rejection determines filter requirements Out-of-Band rejection determines audible noise Integrated Out-of-band noise generated by DAC during normal PCM audio playback over: BW = 28.8 KHz~100 KHz, with respect to 1 VRMS DAC output
Revision 1.5, October 11, 2002
31
Data Sheet
VT1616 6-Channel AC97 Codec with S/PDIF Performance Specifications (continued...)
Table 10. Analog Performance Characteristics (+3.3V Power)
TA=25C, AVCC = DVCC = 3.3V 5%; AGND = DGND =0V; 10k / 50pF Load; FS = 48 KHz, 0dB = 0.70VRMS; BW: 20Hz ~ 20 KHz, 0dB Attentuation, IB[1:0]=10 (set by software), as targeted for a 2-layers VT5542 ACR card
Symbol
Parameter
Full Scale Input Voltage: Line Inputs Mic Inputs (20dB = 0) Mic Inputs (20dB = 1) Full Scale Output Voltage: Analog S/N: Analog Frequency Response Digital S/N: Total Harmonic Distortion: D/A and A/D Frequency Response: Transition Band: Stop Band: Stop Band Rejection: Out-of-Band Rejection Group Delay Power Supply Rejection Ration (1 KHz) Input Channel Crosstalk Spurious Tone Reduction Attenuation, Gain Step Size Input Impedance Input Capacitance VREFOUT DACs ADC Line Outputs DACs ADC DACs ADCs DACs ADC DACs ADC Line Outputs Mono Output CD to LINE_OUT Other to LINE_OUT
Min
Typ
0.7 0.7 0.07 0.70 0.07 92 92
Max
Unit
VRMS VRMS VRMS VRMS VRMS dB dB
20 85 88 -70 20 20 19,200 19,200 28,800 28,800 TBD TBD -40
20,000
Hz dB dB dB
19,200 19,200 28,800 28,800 infinity infinity
Hz Hz Hz Hz Hz Hz dB dB dB
1 -40 -70 -100 1.5 10 50 15 1.5
ms dB dB dB dB k pF V
Note:
VIL = 0.8V, VIH = 2.4V Analog Frequency Response has 1dB limits SNR (measured as THD+N) of rms output level with 1 KHz full-scale input to rms output level with all zeros into digital input Measured "A wtd" over a 20Hz ~ 20 KHz bandwidth (AES17-1991 Idle Channel Noise or EIAJ CP-307 SNR) THD: 0dB gain, 20 KHz BW, Fs = 48 KHz, -3dB "large" signal A/D and D/A Frequency Response has 0.25dB limits Stop Band Rejection determines filter requirements Out-of-Band rejection determines audible noise Integrated Out-of-band noise generated by DAC during normal PCM audio playback over: BW = 28.8 KHz~100 KHz, with respect to 0.70 VRMS DAC output
Revision 1.5, October 11, 2002
32
Data Sheet
VT1616 6-Channel AC97 Codec with S/PDIF Performance Specifications (continued...)
Table 11. Miscellaneous Analog Performance Characteristics
(TA=25C, AVCC = 5.0V 5%, DVCC = 3.3V 5%; AGND = DGND =0V; 10k / 50pF Load); FS = 48 KHz, 0dB = 1VRMS; BW: 20Hz ~ 20 KHz, 0dB Attentuation)
Symbol
Mixer Gain Range Span:
Parameter
LINE_IN, AUX, VIDEO, MIC1, MIC2, PHONE, PC_BEEP LINE_OUT, MONO_OUT Mixer Step Size: All Volume Controls except PC_BEEP PC_BEEP Mixer Mute Level Mixer Gain: Interchannel Gain Mismatch Gain Drift ADC and Analog Inputs (Rs=50) Resolution Gain Error Offset Error Input Impedance DAC and Analog Outputs: Resolution Interchannel Isolation Interchannel Gain Mismatch Gain Error Gain Drift
Min
Typ
46.5 46.5 1.5 3.0 110
Max
Unit
dB dB dB dB dB
-0.5 100
0.5 18 2 10 50 18 80 0.1 60 0.2 5 5
dB ppm/C bits % mV k bits dB dB % ppm/C
Revision 1.5, October 11, 2002
33
Data Sheet
VT1616 6-Channel AC97 Codec with S/PDIF Electrical Specifications
Table 12. DC Characteristics
(TA=25C, AVCC = 5.0V 5%, DVCC = 3.3V 5%; AGND = DGND =0V; 50pF Load)
Symbol
VIN VIL VIH VOL VOH - - - Input Voltage Range Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
Parameter
Min
-0.3
Typ
Max
Vcc+0.3 0.3 x Vcc
Unit
V V V
0.7 x Vcc 0.4 2.4 -10 -10 TBD 10 10
V V A A mA
Input Leakage Current (AC-Link) Output Leakage Current (AC-Link and Hi-Z) Output Buffer Drive Current
Table 13. Power Consumption (+5V Power)
(TA=25C, AVCC = 5.0V 5% DVCC = 3.3V 5%; AGND = DGND =0V; 50pF Load)
Symbol
IVCC IVCC IVCC IVCC IVCC IVCC IAVCC IAVCC IAVCC IAVCC IAVCC IAVCC
Parameter
Digital Supply Current: Power Up (default) All active (2Ah = 0004h) S/PDIF on (2Ah = 3804h) All DACs off (PR1, 26h = 0200h, 2Ah = 3800h) PR4 (26h =1F00h, 2Ah = 3800h) Power Down (PR6, RESET# = 0) Analog Supply Current: Power Up (default) All active (2A = 0004h) PR0 (26h = 0100h, i.e. ADC off) All DACs off (PR1, 26h = 0200h, 2Ah = 3800h) PR2 (26h = 0700h) Power Down (PR3, 26h = 0F00h, 2Ah = 3800h)
Min
Typ
27 38 33 14 0.5 0.08 42 52 42 37 16 3
Max
Unit
mA mA mA mA mA mA mA mA mA mA mA mA
Table 14. Power Consumption (+3.3V Power)
(TA=25C, AVCC = DVCC = 3.3V 5%; AGND = DGND =0V; 50pF Load)
Symbol
IVCC IVCC IAVCC IAVCC IAVCC
Parameter
Digital Supply Current: Power Up Digital Supply Current: Power Down Analog Supply Current: Power Up default Analog Supply Current: Power Up, IB[1:0]=11 Analog Supply Current: Power Down, IB[1:0]=xx
Min
Typ
TBD TBD TBD TBD TBD
Max
Unit
mA mA mA mA mA
Revision 1.5, October 11, 2002
34
Data Sheet
VT1616 6-Channel AC97 Codec with S/PDIF AC Timing Characteristics
(Test Conditions: TA=25C, AVCC = 5.0V 5%, DVCC = 3.3V 5%; AGND = DGND =0V; 50pF Load)
Table 15. Cold Reset
Symbol
TRST_LOW TRST2CLK
Parameter
RESET# Active Low Pulse Width RESET# Inactive to BIT_CLK Startup Delay
Min
1 162.8
Typ
Max
Unit
s ns
TRST_LOW
RESET#
TRST2CLK
BIT_CLK
Figure 7. Cold Reset Timing
Table 16. Warm Reset
Symbol
TSYNC_HIGH TSYNC2CLK
Parameter
Sync Active High Pulse Width SYNC Inactive to BIT_CLK Startup Delay
Min
Typ
1.3
Max
Unit
s ns
162.8
TSYNC_HIGH
SYNC
TSYNC2CLK
BIT_CLK
Figure 8. Warm Reset Timing
Revision 1.5, October 11, 2002
35
Data Sheet
VT1616 6-Channel AC97 Codec with S/PDIF
Table 17. BIT_CLK Timing
Symbol
BIT_CLK Frequency TCLK_PERIOD TCLK_HIGH TCLK_LOW TCLK_DC BIT_CLK Period BIT_CLK Output Jitter BIT_CLK Pulse Width (high) BIT_CLK Pulse Width (low) BIT_CLK Duty Cycle 32.56 32.56 40 40.7 40.7
Parameter
Min
Typ
12.288 81.4
Max
Unit
MHz ns
750 48.84 48.84 60
ps ns ns %
TCLK_HIGH
BIT_CLK
TCLK_LOW
TCLK_PERIOD Figure 9. BIT_CLK Timing
Table 18. SYNC Timing
Symbol
SYNC Frequency TSYNC_PERIOD SYNC Period TSYNC_HIGH TSYNC_LOW SYNC Pulse Width (high) SYNC Pulse Width (low)
Parameter
Min
Typ
48 20.8 1.3 19.5
Max
Unit
KHz s s s
TSYNC_HIGH = 16 TCLK_PERIOD TSYNC_LOW= 240 TCLK_PERIOD
SYNC
TSYNC_PERIOD
Figure 10. SYNC Timing
Revision 1.5, October 11, 2002
36
Data Sheet
VT1616 6-Channel AC97 Codec with S/PDIF
Table 19. Setup and Hold Timing
Symbol
TSETUP1 THOLD1 TSETUP2 THOLD2 Note:
Parameter
SDATA_OUT Setup to falling edge of BIT_CLK SDATA_OUT Hold from falling edge of BIT_CLK SYNC Setup to rising edge of BIT_CLK SYNC Hold to rising edge of BIT_CLK
Min
15 5 15 5
Typ
Max
Unit
ns ns ns ns
SDATA_IN setup and hold calculations determined by AC'97 controller propagation delay.
TSETUP1
BIT_CLK SDATA_IN
THOLD1
SDATA_OUT SYNC
TSETUP2 Figure 11. Setup and Hold Timing
THOLD2
Table 20. Rise and Fall Timing
Symbol
TRISE TFALL TRISE TFALL TRISE TFALL TRISE TFALL BIT_CLK rise time BIT_CLK fall time SYNC rise time SYNC fall time SDATA_IN rise time SDATA_OUT fall time SDATA_OUT rise time SDATA_OUT fall time
Parameter
Min
2 2 2 2 2 2 2 2
Typ
Max
6 6 6 6 6 6 6 6
Unit
ns ns ns ns ns ns ns ns
BIT_CLK, SYNC SDATA_IN, SDATA_OUT
TRISE
TFALL
Figure 12. Rise Time and Fall Timing
Revision 1.5, October 11, 2002 37 Data Sheet
VT1616 6-Channel AC97 Codec with S/PDIF
Table 21. AC Link Low Power Mode
Symbol
TS2_PDOWN Note:
Parameter
End of Slot 2 to BIT_CLK / SDATA_IN low
Min
Typ
Max
1
Unit
s
BIT_CLK not to scale.
SYNC
Slot 1
Slot 2
BIT_CLK
TS2_PDOWN
SDATA_OUT
SDATA_IN
Figure 13. AC Link Power Mode Timing
Revision 1.5, October 11, 2002
38
Data Sheet
VT1616 6-Channel AC97 Codec with S/PDIF
Table 22. ATE Test Mode Timing
Symbol Parameter Min
15 25
Typ
Max
Unit
ns ns
TSETUP2RST SDATA_OUT setup to RESET# rising edge TOFF RESET# rising edge to Hi-Z state
TSETUP2RST
RESET# SDATA_OUT SDATA_IN, BIT_CLK
Hi-Z TOFF Figure 14. ATE Test Mode Timing
Table 23. Vendor Test Mode Timing
Symbol Parameter Min
15 25
Typ
Max
Unit
ns ns
TSETUP2RST SYNC setup to RESET# rising edge TOFF RESET# rising edge to Hi-Z state
TSETUP2RST
RESET#
SYNC
BIT_CLK
Hi-Z TOFF Figure 15. Vendor Test Mode Timing
Revision 1.5, October 11, 2002
39
Data Sheet
VT1616 6-Channel AC97 Codec with S/PDIF Package Dimensions
A B
Pin 1 Identifier
Part Number Date Code and Chip Version Lot Code
VT1616 YYMMVV LLLLLLLLL C
D
C
M
J E I K F G H
Mechanical Dimensions
Symbol
48-pin (7x7) LQFP minimum maximum 8.6 9.4 6.9 7.1 8.6 9.4 6.9 7.1 0 0.5 10 0.28 0.15 1.7 0.7 0.175 0.13 0.05 - 0.3 0.100
A
B
C
D
E
F
G
H
I
J
K
Dimensions above are in millimeters, unless otherwise stated
Revision 1.5, October 11, 2002
40
Data Sheet

▲Up To Search▲

Price & Availability of VT1616

	To Download VT1616 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .